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| DRAM MODULE KMM5364003CK/CKG KMM5364103CK/CKG 4Byte 4Mx36 SIMM (4Mx4 & 16M Quad CAS base) Revision 0.1 Nov. 1997 DRAM MODULE Revision History Version 0.1 (Nov. 1997) * Changed the mode of parity check component from EDO to FP, refer to KMM5364003CK/CKG KMM5364103CK/CKG PACKAGE DIMENSIONS and GENERAL DISCRIPTION. DRAM MODULE KMM5364003CK/CKG KMM5364103CK/CKG KMM5364003CK/CKG & KMM5364103CK/CKG with Fast Page Mode 4M x 36 DRAM SIMM using 4Mx4 and 16M Quad CAS, 4K/2K Refresh, 5V GENERAL DESCRIPTION The Samsung KMM53640(1)03CK is a 4Mx36bits Dynamic RAM high density memory module. The Samsung KMM53640(1)03CK consists of eight CMOS 4Mx4bits DRAMs in 24-pin SOJ package and one CMOS 4Mx4 bit Quad CAS DRAM in 28-pin SOJ package mounted on a 72-pin glassepoxy substrate. A 0.1 or 0.22uF decoupling capacitor is mounted on the printed circuit board for each DRAM. The KMM53640(1)03CK is a Single In-line Memory Module with edge connections and is intended for mounting into 72 pin edge connector sockets. FEATURES * Part Identification - KMM5364003CK(4096 cycles/64ms Ref, SOJ, Solder) - KMM5364003CKG(4096 cycles/64ms Ref, SOJ, Gold) - KMM5364103CK(2048 cycles/32ms Ref, SOJ, Solder) - KMM5364103CKG(2048 cycles/32ms Ref, SOJ, Gold) * Fast Page Mode Operation * CAS-before-RAS refresh capability * RAS-only and Hidden refresh capability * TTL compatible inputs and outputs * Single +5V 10% power supply * JEDEC standard PDPin & pinout * PCB : Height(1000mil), single sided component PERFORMANCE RANGE Speed -5 -6 tRAC 50ns 60ns tCAC 13ns 15ns tRC 90ns 110ns PIN CONFIGURATIONS Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Symbol VSS DQ0 DQ18 DQ1 DQ19 DQ2 DQ20 DQ3 DQ21 Vcc NC A0 A1 A2 A3 A4 A5 A6 A10 DQ4 DQ22 DQ5 DQ23 DQ6 DQ24 DQ7 DQ25 A7 A11 Vcc A8 A9 Res(RAS1) RAS0 DQ26 DQ8 Pin 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Symbol DQ17 DQ35 Vss CAS0 CAS2 CAS3 CAS1 RAS0 Res(RAS1) NC W NC DQ9 DQ27 DQ10 DQ28 DQ11 DQ29 DQ12 DQ30 DQ13 DQ31 Vcc DQ32 DQ14 DQ33 DQ15 DQ34 DQ16 NC PD1 PD2 PD3 PD4 NC Vss PIN NAMES Pin Name A0 - A11 A0 - A10 DQ0 - DQ35 W RAS0 CAS0 - CAS3 PD1 -PD4 Vcc Vss NC Function Address Inputs(4K Ref) Address Inputs(2K Ref) Data In/Out Read/Write Enable Row Address Strobe Column Address Strobe Presence Detect Power(+5V) Ground No Connection PRESENCE DETECT PINS (Optional) Pin PD1 PD2 PD3 PD4 50NS Vss NC Vss Vss 60NS Vss NC NC NC * Pin connection changing available SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. * NOTE : A11 is used for only KMM5364003CK/CKG (4K ref.) DRAM MODULE FUNCTIONAL BLOCK DIAGRAM CAS0 RAS0 CAS RAS OE U0 W DQ0 DQ1 DQ2 A0A11(A10) DQ3 DQ0 DQ1 DQ2 A0A11(A10) DQ3 DQ0 DQ1 DQ2 A0A11(A10) DQ3 DQ0 DQ1 DQ2 A0A11(A10) DQ3 DQ0 DQ1 DQ2 A0A11(A10) DQ3 DQ0 DQ1 DQ2 A0A11(A10) DQ3 DQ0 DQ1 DQ2 A0A11(A10) DQ3 DQ0 DQ1 DQ2 A0A11(A10) DQ3 KMM5364003CK/CKG KMM5364103CK/CKG DQ0-DQ3 CAS RAS OE U1 W DQ4-DQ7 CAS1 CAS RAS OE U2 W DQ9-DQ12 CAS RAS OE U3 W DQ13-DQ16 CAS2 CAS RAS OE U4 W DQ18-DQ21 CAS RAS OE U5 W DQ22-DQ25 CAS3 CAS RAS OE U6 W DQ27-DQ30 CAS RAS OE U7 W DQ31-DQ34 CAS0 CAS1 CAS2 CAS3 RAS OE W W A0-A11(A10) Vcc U8 DQ0 DQ1 DQ2 DQ3 DQ8 DQ17 DQ26 DQ35 A0A11(A10) .1 or .22uF Capacitor for each DRAM Vss To all DRAMs DRAM MODULE ABSOLUTE MAXIMUM RATINGS * Item Voltage on any pin relative to V SS Voltage on V CC supply relative to V SS Storage Temperature Power Dissipation Short Circuit Output Current Symbol VIN, VOUT VCC Tstg Pd IOS KMM5364003CK/CKG KMM5364103CK/CKG Rating -1 to +7.0 -1 to +7.0 -55 to +150 9 50 Unit V V C W mA * Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for in tended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (Voltage referenced to V SS, TA = 0 to 70C) Item Supply Voltage Ground Input High Voltage Input Low Voltage *1 : VCC+2.0V/20ns, Pulse width is measured at VCC. *2 : -2.0V/ 20ns, Pulse width is measured at VSS. Symbol VCC VSS VIH VIL Min 4.5 0 2.4 -1.0 *2 Typ 5.0 0 Max 5.5 0 VCC+1 *1 0.8 Unit V V V V DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted) Symbol ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 II(L) IO(L) VOH VOL ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 II(L) IO(L) VOH VOL Speed -5 -6 Dont care -5 -6 -5 -6 Dont care -5 -6 Dont care Dont care KMM5364003CK/CKG Min - KMM5364103CK/CKG Min - Max 810 720 18 810 720 720 630 9 810 720 45 5 0.4 Max 990 900 18 990 900 810 720 9 990 900 45 5 0.4 Unit mA mA mA mA mA mA mA mA mA mA uA uA V V -45 -5 2.4 - - - -45 -5 2.4 - : Operating Current * ( RAS, CAS, Address cycling @ tRC=min) : Standby Current ( RAS=CAS=W=VIH) : RAS Only Refresh Current * ( CAS=VIH, RAS cycling @ tRC=min) : Fast Page Mode Current * ( RAS=VIL, CAS Address cycling : tPC=min) : Standby Current ( RAS=CAS=W=Vcc-0.2V) : CAS-Before-RAS Refresh Current * ( RAS and CAS cycling @ tRC=min) : Input Leakage Current (Any input 0 VINVcc+0.5V, all other pins not under test=0 V) : Output Leakage Current(Data Out is disabled, 0V VOUTVcc) : Output High Voltage Level (I OH = -5mA) : Output Low Voltage Level (I OL = 4.2mA) * NOTE : ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In I CC1 and ICC3, address can be changed maximum once while RAS=VIL. In ICC4, address can be changed maximum once within one page mode cycle, tPC. DRAM MODULE CAPACITANCE (TA = 25C, VCC=5V, f = 1MHz) Item Input capacitance[A0-A11(A10)] Input capacitance[ W] Input capacitance[ RAS0] Input capacitance[ CAS0 - CAS3] Input/Output capacitance[DQ0-35] Symbol CIN1 CIN2 CIN3 CIN4 CDQ Min - KMM5364003CK/CKG KMM5364103CK/CKG Max 65 80 80 40 25 Unit pF pF pF pF pF AC CHARACTERISTICS (0CTA70C, VCC=5.0V10%. See notes 1,2.) Test condition : Vih/Vil=2.4/0.8V, V oh/Vol=2.4/0.4V, Output loading CL=100pF Parameter Random read or write cycle time Access time from RAS Access time from CAS Access time from column address CAS to output in Low-Z Output buffer turn-off delay Transition time(rise and fall) RAS precharge time RAS pulse width RAS hold time CAS hold time CAS pulse width RAS to CAS delay time RAS to column address delay time CAS to RAS precharge time Row address set-up time Row address hold time Column address set-up time Column address hold time Column address to RAS lead time Read command set-up time Read command hold time referenced to CAS Read command hold time referenced to RAS Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data-in set-up time Data-in hold time Refresh period (4K Ref) Refresh period (2K Ref) Write command set-up time CAS setup time( CAS-before-RAS refresh) CAS hold time( CAS-before-RAS refresh) RAS precharge to CAS hold time Symbol -5 Min 90 50 13 25 0 0 3 30 50 13 50 13 20 15 5 0 10 0 10 25 0 0 0 10 10 13 13 0 10 64 32 0 5 10 5 0 5 10 5 10K 37 25 10K 13 50 0 0 3 40 60 15 60 15 20 15 5 0 10 0 10 30 0 0 0 10 10 15 15 0 15 64 32 10K 45 30 10K 15 50 Max Min 110 60 15 30 -6 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms ns ns ns ns 7 9 9 8 8 4 10 3,4 3,4,5 3,10 3 6 2 Note tRC tRAC tCAC tAA tCLZ tOFF tT tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH tWCH tWP tRWL tCWL tDS tDH tREF tREF tWCS tCSR tCHR tRPC DRAM MODULE AC CHARACTERISTICS (0CTA70C, VCC=5.0V10%. See notes 1,2.) Test condition : Vih/Vil=2.4/0.8V, V oh/Vol=2.4/0.4V, Output loading CL=100pF Parameter Access time from CAS precharge Fast page mode cycle time CAS precharge time(Fast page cycle) RAS pulse width(Fast page cycle) W to RAS precharge time(C-B-R refresh) W to RAS hold time(C-B-R refresh) Hold time CAS low to CAS high Symbol -5 Min 35 10 50 10 10 5 200K Max 30 KMM5364003CK/CKG KMM5364103CK/CKG -6 Min 40 10 60 10 10 5 200K Max 35 Unit ns ns ns ns ns ns ns Note 3 tCPA tPC tCP tRASP tWRP tWRH tCLCH 11 NOTES 1. An initial pause of 200us is required after power-up followed by any 8 RAS-only or CAS-before-RAS refresh cycles before proper device operation is achieved. 2. VIH(min) and V IL(max) are reference levels for measuring timing of input signals. Transition times are measured between V IH(min) and V IL(max) and are assumed to be 5ns for all inputs. 3. Measured with a load equivalent to 2 TTL loads and 100pF. 4. Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC. 5. Assumes that tRCDtRCD(max). 6. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to V OH or VOL. 7. tWCS is non-restrictive operating parameter. It is included in the data sheet as electrical characteristic s only. If tWCStWCS(min), the cycle is an early write cycle and the data out pin will remain high impedance for the duration of the cycle. 8. Either tRCH or tRRH must be satisfied for a read cycle. 9. These parameter are referenced to the CAS leading edge in early write cycles. 10. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as reference point only. If tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA. 11. In order to hold the address latched by the first CAS going low, the parameter tCLCH must be met. DRAM MODULE READ CYCLE KMM5364003CK/CKG KMM5364103CK/CKG tRC tRAS RAS VIH VIL - tRP tCSH tCRP CAS VIH VIL - tRCD tRSH tCAS tRAL tCAH COLUMN ADDRESS tCRP tRAD tASR A VIH VIL - tRAH tASC ROW ADDRESS tRCS W VIH VIL - tRCH tRRH tAA tCAC tCLZ DATA-OUT tOFF DQ VOH VOL - tRAC OPEN Dont care Undefined DRAM MODULE WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN KMM5364003CK/CKG KMM5364103CK/CKG tRAS RAS VIH VIL - tRC tRP tCSH tCRP CAS VIH VIL - tRCD tRSH tCAS tRAL tCAH COLUMN ADDRESS tCRP tRAD tASR A VIH VIL - tRAH tASC ROW ADDRESS tCWL tRWL tWCS W VIH VIL - tWCH tWP tDS DQ VIH VIL - tDH DATA-IN Dont care Undefined DRAM MODULE FAST PAGE READ CYCLE NOTE : DOUT = OPEN KMM5364003CK/CKG KMM5364103CK/CKG tRASP RAS VIH VIL o tRP tRHCP tCRP CAS VIH VIL - tPC tRCD tCAS tRAD tASC tCSH tCAH COLUMN ADDRESS tCP tCAS o tCP tRSH tCAS tASR A VIH VIL ROW ADDR tRAH tASC tCAH o o tASC tCAH COLUMN ADDRESS COLUMN ADDRESS tRRH tRCS W VIH VIL - tRCH tRCS o tRCS tRCH tCAC tAA tRAC tCLZ VALID DATA-OUT tCAC tAA tOFF tCLZ VALID DATA-OUT tCAC tAA tOFF tCLZ VALID DATA-OUT tOFF DQ VOH VOL - Dont care Undefined DRAM MODULE FAST PAGE WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN KMM5364003CK/CKG KMM5364103CK/CKG tRASP RAS VIH VIL o tRP tRHCP tCRP CAS VIH VIL - tPC tRCD tCAS tRAD tASC tCP tCAS o tPC tCP tRSH tCAS tASR A VIH VIL - tRAH tCSH tCAH COLUMN ADDRESS tASC tCAH o o tASC tCAH ROW ADDR COLUMN ADDRESS COLUMN ADDRESS tWCS W VIH VIL - tWCH tWP tCWL tWCS tWP tCWL tDS tWCH o tWCS tWCH tWP tCWL tRWL tDH tDS DQ VIH VIL - tDH tDH o tDS VALID DATA-IN VALID DATA-IN o VALID DATA-IN Dont care Undefined DRAM MODULE RAS - ONLY REFRESH CYCLE NOTE : W, OE, DIN = Dont care DOUT = OPEN tRC KMM5364003CK/CKG KMM5364103CK/CKG tRAS RAS VIH VIL - tRP tCRP CAS VIH VIL - tRPC tCRP tASR A VIH VIL ROW ADDR tRAH CAS - BEFORE - RAS REFRESH CYCLE NOTE : OE, A = Dont care tRC tRP RAS VIH VIL - tRAS tRP tRPC tCP tRPC tCSR tWRP tWRH tCHR CAS VIH VIL - W VIH VIL - tOFF DQ VOH VOL - OPEN Dont care Undefined DRAM MODULE HIDDEN REFRESH CYCLE ( READ ) KMM5364003CK/CKG KMM5364103CK/CKG tRC tRAS RAS VIH VIL - tRC tRP tRAS tRP tCRP CAS VIH VIL - tRCD tRSH tCHR tRAD tASR A VIH VIL - tRAH tASC tCAH COLUMN ADDRESS ROW ADDRESS tWRH tRCS W VIH VIL - tRRH tWRP tAA tCAC tCLZ DATA-OUT tOFF tRAC DQ VOH VOL - OPEN Dont care Undefined DRAM MODULE HIDDEN REFRESH CYCLE ( WRITE ) NOTE : DOUT = OPEN KMM5364003CK/CKG KMM5364103CK/CKG tRC RAS VIH VIL - tRC tRP tRAS tRP tRAS tCRP CAS VIH VIL - tRCD tRAD tRSH tCHR tASR A VIH VIL - tRAH tASC tCAH COLUMN ADDRESS ROW ADDRESS tWRH tWRP W VIH VIL - tWCS tWP tWCH tDS DQ VIH VIL - tDH DATA-IN Dont care Undefined DRAM MODULE CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE KMM5364003CK/CKG KMM5364103CK/CKG tRP RAS VIH VIL VIH VIL - tRAS tCPT tCHR tRSH tCAS tRAL tASC tCAH tCSR CAS A VIH VIL - COLUMN ADDRESS READ CYCLE W VIH VIL - tWRP tWRH tRCS tAA tCAC tRRH tRCH DQ VOH VOL - tCLZ DATA-OUT tOFF WRITE CYCLE W VIH VIL - tWRP tWRH tWCS tRWL tCWL tWCH tWP tDS tDH DATA-IN DQ VIH VIL - OPEN Dont care Undefined NOTE : This timing diagram is applied to all devices besides 16M DRAM 4th & 64M DRAM. DRAM MODULE CAS - BEFORE - RAS SELF REFRESH CYCLE NOTE : OE, A = Dont care KMM5364003CK/CKG KMM5364103CK/CKG tRP RAS VIH VIL - tRASS tRPS tRPC tCHS tRPC tCP CAS VIH VIL - tCSR tOFF DQ VOH VOL - OPEN tWRP tWRH W VIH VIL - TEST MODE IN CYCLE NOTE : OE, A = Dont care tRC tRP RAS VIH VIL - tRAS tRP tRPC tCP tRPC tCSR tWTS tWTH tCHR CAS VIH VIL - W VIH VIL - tOFF DQ VOH VOL - OPEN Dont care Undefined DRAM MODULE PACKAGE DIMENSIONS KMM5364003CK/CKG KMM5364103CK/CKG Units : Inches (millimeters) 4.250(107.95) 3.984(101.19) .133(3.38) R.062(1.57) .125 DIA.002(3.18.051) .400(10.16) 1.00(25.40) .250(6.35) .080(2.03) .250(6.35) .250(6.35) 3.750(95.25) R.062.004(R1.57.10) .125(3.17) MIN ( Front view ) ( Back view ) Gold & Solder Plating Lead .200(5.08) MAX .010(.25)MAX .100(2.54) MIN .050(1.27) .041.004(1.04.10) .054(1.37) .047(1.19) Tolerances : .005(.13) unless otherwise specified NOTE : The used device are 4Mx4 FP DRAM (SOJ & 300mil) & 4Mx4 Quad CAS with FP DRAM (SOJ & 300mil) DRAM Part No. : KMM5364003CK/CKG -- KM44C4000CK (300 mil) & KM44C4003CK (300mil) KMM5364103CK/CKG -- KM44C4100CK (300 mil) & KM44C4103CK (300mil) Revision History Rev 0.1 : Nov. 1997 |
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